Different types of memory are used in electronic apparatus for various purposes. Read-Only Memory (ROM) and Random Access Memory (RAM) are two such types of memory commonly used within computers for different memory functions. ROM retains its stored data when power is switched off and therefore is often employed to store programs that are needed for initializing (colloquially, “booting up”) an apparatus. ROM, however, does not accommodate writing. RAM, on the other hand, allows data to be written to or read from selected addresses associated with memory cells and, therefore, is typically used during normal operation of the apparatus.
Two common types of RAM are dynamic RAM (DRAM) and static RAM (SRAM). DRAM is typically used for the main memory of computers or other electronic apparatuses since, though it must be refreshed, it is typically inexpensive and requires less chip space than SRAM. Though more expensive and space-consumptive, SRAM does not require refreshing thereby making it a faster memory option. In addition, SRAM may use metal-oxide-semiconductor (MOS) technology, allowing it to have a relatively low standby power. These attributes make SRAM devices particularly desirable for portable equipment, such as laptop computers and personal digital assistants.
A typical SRAM device includes a matrix of addressable memory cells arranged in columns and rows and referred to as an SRAM array. A typical memory cell includes two access transistors and a flip-flop having two memory transistors and two loads. The gates of the access transistors in each row are connected to a word line and the sources of each access transistor are connected to either one of a bit line pair, B or {overscore (B)}. Peripheral circuitry associated with the rows (or word lines) and peripheral circuitry associated with the columns (or bit lines) facilitate reading data from, and writing data to, the memory cells.
Column periphery circuitry includes main column peripheral driving circuitry and main column peripheral circuitry. Typically, the main column peripheral driving circuitry drives an associated main column peripheral circuitry. For example, main pre-charge driving circuitry is configured to drive main pre-charge circuitry for the SRAM array. Additionally, the SRAM device includes a controller having column periphery control drivers. The column periphery control drivers are typically configured to drive the main column peripheral driving circuitry such as the main pre-charge driving circuitry.
Generally, to read data from a memory cell, a word line driver may activate a word line according to an address decoded by a row decoder and received via a row signal path that typically includes an address bus connected to the SRAM device. The access transistors turn on and connect the outputs of the flip-flop to the bit line pair sending signals representing the data in the memory cell to a sense amplifier coupled to the bit line pair that amplifies the potential difference thereon. After the data is stabilized, a column decoder selects the corresponding column, or bit line pair, and outputs a data signal to a data output buffer and then to the external circuitry of the associated electronic apparatus. Essentially, data may be written to each memory cell in an opposite way.
As mentioned above, to retain the data written to the matrix of memory cells, or memory array, each memory cell must have a continuous supply of power. SRAM devices, however, are often employed within battery-powered wireless apparatus where power consumption is an important design parameter. Accordingly, wireless apparatus may be transitioned from an active or idle mode to a standby mode of lower power consumption. As transistor size continues to diminish (e.g., 90 nm transistors), current leakage may be unacceptably high even during standby mode, requiring a transition to a still lower power consumption level, a data retention or sleep mode, to conserve power adequately. The battery-powered wireless apparatus, therefore, may power-down the row and column circuitry associated with the memory array and enter the sleep mode while still supplying sufficient power to the memory array to retain data.
Presently, various powering-down designs for the peripheral circuitry are used. Typically, each of the various designs seek a balance among complexity, reliability and minimum power consumption during the sleep mode. To achieve absolute minimum power during the sleep mode, all of the peripheral circuitry may be powered-down while sufficient power to the memory array is maintained. Additionally, powering-down designs may also strive to reduce voltage fluctuations, or “wiggling,” in word lines caused by the peripheral circuitry while transitioning from standby to sleep mode to prevent false reads or writes on the word line. Once the sleep mode has been entered, additional problems may be encountered. For example, currents may leak from the memory array to the peripheral circuitry associated with the columns.
In some existing SRAM devices, powering-down to the sleep mode may be completed by employing a single switch pair to control power for the SRAM device. One design to minimize memory array leakage during sleep mode calls for keeping the bit lines floating (at a floating voltage typically near the word line voltage) or clamped at a raised low array voltage supply, VSB, level while the word lines are maintained at either the low power supply, VSS, level or the VSB level or there between. In some SRAM devices, SRAM headers or footers (those local to the SRAM) may be coupled in series with main column peripheral circuitry to float the bit lines. Alternatively, the main column peripheral circuitry may be isolated from the bit lines by inserting isolation transistors in series with main pre-charge circuitry, main write circuitry, main column multiplexers, and main sense amplifiers for each bit line. Undesirably, a significant amount of gate and subthreshold current leakage among some of the large column periphery transistors whose gate, drain, and source are at different potentials (e.g., 0.8 volts versus 0.0 volts) may still occur, and the added transistors in series with the main column periphery circuitry result in lower performance for the column periphery circuitry and the SRAM device.
Accordingly, what is needed in the art is an improved high performance low-power SRAM device that maintains high performance during active mode while minimizes current leakage during sleep mode and an improved method of powering-down an SRAM device to the sleep mode. More specifically, what is needed in the art is an improved SRAM device that isolates bit lines without negatively impacting the performance of the SRAM's column periphery circuitry.